The course discusses state-of-the-art methodologies and
algorithms for VLSI physical and logic-level design automation. The discussed
CAD methods contemplate various performance aspects, such as
silicon area, timing, power consumption, noise, and crosstalk. Project assignments
include software development for each of the studied tasks.
Upon completion of
the course, students will know to develop and implement modern algorithms
for VLSI logic and physical level design. The studied
CAD techniques address design tasks such as partitioning, floorplanning,
module placement, and signal routing. Automated optimization of combinational
and sequential circuits will be also studied.
Monday, Wednesday 1-3pm (Light Engineering Bldg. 261).
Lecture 1 (week 1): VLSI Physical Design
Design and fabrication of VLSI chips.
Basic data structures & algorithms.
Lecture 2 (week 2-3): Partitioning .
Lecture 3 (week 4): Placement and floorplanning .
Lecture 4 (week 5): Global routing .
Lecture 5 (week 6): Detailed routing .
Lecture 6 (week 7): Specialized routing .
Lecture 7 (week 9): Floorplanning, placement and routing for analog and mixed-signal designs.
Lecture 8 (week 10): Two-level combinational logic optimization. Exact optimization algorithms. Heuristic optimization algorithms.
Lecture 9 (week 11): Multi-level combinational logic optimization. . Timing issues.
Lecture 10 (week 13): Sequential logic optimization.
Lecture 11 (week 14): Cell-library binding.
Lecture 12 (week 15): Current research problems in logic-level CAD.
Mini project 1: Partitioning: starts February 7 2006 - due February 23 2006.
Mini project 2: Placement and global routing: starts March 7 2006 - due March 30 2006.
Mini project 3: Logic optimization: starts March 30 2006 - due May 4 2006.
Midterm : Thursday, March 9 2006 - 3.50-5.10pm
Final exam : Exam week
Final Grade = Project1 * 0.1 + Project 2 * 0.2 + Project3 * 0.2 + Midterm * 0.2 + Final * 0.3
If you want to share comments or anything else related to the class please send an e-mail to Alex Doboli . Last updated Feb 7 2006.