Project Description

Develop, implement and experiment a placement algorithm having the following characteristics:                                                                      

Objective	Simulated annealing	Partitioning based
Minimize total wirelength	Group 1, Group 3, Group 5, Group 7, Group 9, Group 11	Group 2, Group 4, Group 6, Group 8, Group 10, Group 12
Minimize length of  longest interconect wire	Group 1, Group 3, Group 5, Group 7, Group 9, Group 11	Group 2, Group 4, Group 6, Group 8, Group 10, Group 12
Routability	Everybody	Everybody
Total IC area is fixed	Group 1, Group 3, Group 5	Group 2, Group 4, Group 6
Minimize total IC area	Group 7, Group 9, Group 11	Group 8, Group 10, Group 12

Inputs

• circuit netlist, area, timing info about each building block, position of I/O pins on the pad frame
• full custom design style is assumed

• you have to decide the interfacing of your software (input/output files, data formats etc)
• the info that should be produced by unroutable layouts to guide the placement process

Benchmark Examples

"Dragon" Benchmark

Marco GSRC T2 Fabric: Bookshelf

What to hand in?

A technical report in hard and soft copy must be handed in.

The report will contain following sections:

• Introduction and Problem Statement.
• Related Work.
• Proposed solution to the problem and relevant implementation issues.
• Experimental results.
• Conclusion.
• Bibliography.