Bryand and O'Hallaron Chapter 3 Section 3.6.1 Condition Codes CF, ZF, SF, and OF Flags 1. CF (Carry Flag) Indicates the most recent result produced a carry out of the high order bit position. Unsigned overflow. CF flag = 1 v 11111 111 carries 1111 1111 255 in binary + 0000 0001 + 1 in binary ----------- ------------- 0000 0000 0 in binary 2. ZF (Zero Flag) Indicates that the most recent result yielded zero (whether overflow occured or not) 11111 111 carries 1111 1111 255 in binary + 0000 0001 + 1 in binary ----------- ------------- 0000 0000 0 in binary ^^^^ ^^^^ all zero, so ZF flag = 1 3. SF (Sign Flag) The most recent result yielded a negative value 11111 111 carries 1111 1111 255 in binary + 0000 0001 + 1 in binary ----------- ------------- 0000 0000 0 in binary ^ SF flag = 0 (not negative) 4. OF (Sign Flag) The most recent result caused a 2's complement overflow. The carry into the high order bit position is different from the out of the high order bit position. carries the same, so OF = 0 (no signed overflow) vv 11111 111 carries 1111 1111 255 in binary + 0000 0001 + 1 in binary ----------- ------------- 0000 0000 0 in binary 5. Unsigned overflow - add to positive numbers and end up with a result that is less than both numbers (e.g. 255 + 1 = 0, 250 + 20 = 14) For a, b, and t unsigned and t=a+b, if t < a (or t < b), unsigned overflow. 6. Signed overflow - If a, b, and t signed and t=a+b, overflow only possible if a and b have the same sign (a < 0 == b < 0). If a and b are both positive (both negative) then t had better be positive (negative) as well. OF = (a < 0 == b < 0) && (t < 0 != a < 0) 6. Signed and unsigned overflow with four bit numbers 7. Signed and unsigned 4-bit arithmetic 1. 16-hour clock face labeled 0000 to 1111. 2. To add one, move hand clockwise one hour. 3. To subtract one, move hand counterclockwase one hour. 4. If you advance hand 16 hours, end up where you started. There must be an error point because X + 16 is not equal to x. Unsigned Arithmetic Signed Arithmetic error \ \ 0000=0 0000=0 \ o o 15=1111 o o 0001=1 -1=1111 o o 0001=1 ^ ^ 14=1110 o | o 0010=2 -2=1110 o | o 0010=2 | | 13=1101 o | o 0011=3 -3=1101 o | o 0011=3 | | | | 12=1100 o o o 0100=4 -4=1100 o o o 0100=4 11=1011 o o 0101=5 -5=1011 o o 0101=5 10=1010 o o 0110=6 -6=1010 o o 0110=6 9=1001 o o 0111=7 -7=1001 o o 0111=7 o o \ 1000=8 1000=-8 \ \ error Load Effective Address leal 7(%edx,%edx,4),%eax #%eax <= 5*%edx + 7 Practice Problem 3.3 Assume %eax holds the value x and %ecx holds the value y. Fill in the table. ______________ leal 6(%eax),%edx ______________ leal (%eax,%ecx),%edx ______________ leal (%eax,%ecx,4),%edx ______________ leal 7(%eax,%eax,8),%edx ______________ leal 0xA(,%ecx,4),%edx ______________ leal 9(%eax,%ecx,2),%edx Figure 3.7 Integer Arithmetic Operations (unary and binary) Instruction Effect Description leal S, D D <- &S Load effective address incl D D <- D + 1 Increment decl D D <- D - 1 Decrement negl D D <- -D Negate notl D D <- ~D Complement addl S, D D <- D + S Add subl S, D D <- D - S Subtract imull S, D D <- D * S Multiply xorl S, D D <- D ^ S Exclusive-or orl S, D D <- D | S Or andl S, D D <- D & S And sall k, D D <- D << k Left shift shll k, D D <- D << k Left shift (just sall) sarl k, D D <- D >> k Arithmetic right shift shrl k, D D <- D >> k Logical right shift Practice Problem 3.4 Assume the following values Address Value Register Value 0x100 0xFF %eax 0x100 0x104 0xAB %ecx 0x1 0x108 0x13 %edx 0x3 0x10c 0x11 Fill in the table Instruction Destination Value addl %ecx,(%eax) subl %edx,4(%eax) imull $16,(%eax,%edx,4) incl 8(%eax) decl %ecx subl %edx,%eax See Practice Problem 3.5 Shift Instructions The amount of the shift can either be specified by an immediate operand or by the contents of register %cl. If there are two opeands, the first must be either an immediate operand or "%cl". In the one operand version, genrates a shift of one bit. The following program assembles without error. .globl main main: sarl $3,%eax # arithmetic left shift by 3 bits movb $3,%cl sarl %cl,%eax # arithmetic left shift, 3 more bits sarl %eax # arithmetic left shift, 1 more bit ret As we have seen, the C complier frequently replaces multiplications by a constant with shifts and adds. 64-bit Multiplications and Divisions Instruction Effect Description imul S R[%edx]:R[%eax] <- S * R[%eax] Signed full multiply mul S R[%edx]:R[%eax] <- S * R[%eax] Unsigned full multiply cltd R[%edx]:R[%eax] <- SignExtend(R[%eax]) Convert to quad word idivl S R[%edx] <- R[%edx]:R[%eax] mod S Signed divide R[%eax] <- R[%edx]:R[%eax] / S divl S R[%edx] <- R[%edx]:R[%eax] mod S Unsigned divide R[%eax] <- R[%edx]:R[%eax] / S Assumed signed numbers x and y stored a 8 and 12 relative to %ebp. To place the full 64-bit product on the top of the stack: move 8(%ebp),%eax # put x in %eax imull 12(%ebp) # multiply by y pushl %edx #push high-order 32 bits pushl %eax #push low-order 32 bits Is the little endian or bit endian? To store x/y and x%y on the stack: move 8(%ebp),%eax # put x in %eax cltd # sign extend into %edx idivl 12(%ebp) # divide by y pushl %eax # push x / y pushl %eax # push x % y