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My research combines aspects of hardware design, digital signal processing, compilers, and computer-aided design of digital systems. The goal of my work is to use domain-specific knowledge of applications in the domain of signal processing (and related areas) to construct automated hardware generation tools (targeting ASIC and FPGA).
I have created and maintain the Spiral DFT/FFT IP Core Generator, an online tool to generate flexible hardware implementations of the discrete Fourier transform suitable for implementation as ASIC or FPGA.
To read more information about my research and tools I have developed or a list of publications with links, please see the menu to your left.