I am looking for motivated PhD students with backgrounds in digital design/FPGAs to join my research group starting Fall 2017. Please contact me if interested.
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My research combines aspects of hardware design, FPGAs, compilers, and CAD, and focuses on applications in machine learning, DSP, and networking.
I have created and maintain the Spiral DFT/FFT IP Core Generator, an online tool to generate flexible hardware implementations of the discrete Fourier transform suitable for implementation as ASIC or FPGA.
To read more information about my research and tools I have developed or a list of publications with links, please see the menu to your left.
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